Processor-based systems, such as computer systems, use memory devices, such as dynamic random access memory (“DRAM”) devices, as system memory to store instructions and data that are accessed by a processor. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read or to which data or instructions are to be written. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data is transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
One approach to increasing the data bandwidth to and from memory devices is to use multiple memory devices coupled to the processor through a memory hub as shown in FIG. 1. A computer system 10 using a memory hub architecture includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108, which, is typically static random access memory (“SRAM”). Finally, the processor bus 106 is coupled to a system controller 110, which is also sometimes referred to as a bus bridge.
The system controller 110 contains a memory hub controller 112 that is coupled to the processor 104. The memory hub controller 112 is also coupled to several memory modules 114a–n through a bus system 115. Each of the memory modules 114a–n includes a memory hub 116 coupled to several memory devices 118 through command, address and data buses 117. The memory hub 116 efficiently routes memory requests and responses between the controller 112 and the memory devices 118. Computer systems employing this architecture can have a higher bandwidth because the processor 104 can access one memory module 114a–n while another memory module 114a–n is responding to a prior memory access. For example, the processor 104 can output write data to one of the memory modules 114a–n in the system while another memory module 114a–n in the system is preparing to provide read data to the processor 104. The operating efficiency of computer systems using a memory hub architecture can make it more practical to vastly increase data bandwidth of a memory system. A memory hub architecture can also provide greatly increased memory capacity in computer systems.
The system controller 110 also serves as a communications path to the processor 104 for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 121, which is, in turn, coupled to a video terminal 123. The system controller 110 is also coupled to one or more input devices 120, such as a keyboard or a mouse, to allow an operator to interface with the computer system 10. Typically, the computer system 10 also includes one or more output devices 122, such as a printer, coupled to the processor 104 through the system controller 110. One or more data storage devices 122 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).
Although there are advantages to utilizing a memory hub for accessing memory devices, the design of the hub memory system, and more generally, computer systems including such a memory hub architecture, becomes increasingly difficult. The memory modules 114a n each internally operate synchronously although operations between memory modules are asynchronous. The command, address, and data signals transferred to the memory module 114a n are normally latched or strobed into the memory modules 114a n by a clock signal. However, as transfer rates increase, the time during which the command, address and data signals as received at the memory hubs 116 are valid decreases. This period during which the signals are valid is commonly referenced by those ordinarily skilled in the art as the “window” or “eye.” Not only does the size of the eye for command, address, and data signals decrease, but the time or location of the eye can also vary because of various factors, such as timing skew, voltage and current drive capability, and the like. In the case of timing skew of signals, it often arises from a variety of timing errors such as loading on the lines of the bus and the physical lengths of such lines.
As the size of signal eyes decrease at higher transfer rates, the variations in the location of the signal eyes become more of a problem. One technique to alleviate this problem to some extent is to couple a clock to the memory modules. As shown in FIG. 1, a clock generator 500 generates a clock signal CLK and couples it to the memory hub controller 112 and each of the memory hubs 116 in respective memory modules 114a–n along with the command, address and data signals that are coupled through the bus system 115. The CLK signal is coupled from the memory hub controller 112 in synchronism with the command, address and data signals so it, in theory, should be usable by the memory hubs 116 to define the eye during for the command, address and data signals as they are received at the memory hubs 116. However, in practice, even this approach becomes ineffective as signal transfer rates continue to decrease. In particular, the CLK signal may be subject to different conditions than the command, address and data signals, such as being coupled through a physically different signal path or being loaded to a greater degree. Also, for the clock forwarding techniques used in the computer system 10 to successfully function at higher clock speeds, the layout of conductors between the memory hub controller 112 and the memory hubs 116 must be precisely controlled.
One technique that has been proposed to allow the CLK signal to continue being used to strobe command, address and data signals at higher transfer rates is to include circuitry (not shown) in the memory hubs 116 that adjusts the timing of the CLK signal within each of the hubs 116 so that it is aligned with the signal eye. However, this technique adds a fair degree of complexity to the memory hubs 116 and is not always effective.
There is therefore a need for a system and method that allows command, address and data signals to be coupled between a memory hub controller and one or more memory hubs in respective memory modules that avoids problems of synchronizing a clock signal coupled between the memory hub controller and memory hubs along with the command, address, and data signals.